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march 2007 rev 5 1/39 1 m29f200bt M29F200BB 2 mbit (256kb x8 or 128kb x16, boot block) single supply flash memory features single 5v10% supply voltage for program, erase and read operations access time: 45, 50, 70, 90ns programming time ? 8s per byte/word typical 7 memory blocks ? 1 boot block (top or bottom location) ? 2 parameter and 4 main blocks program/erase controller ? embedded byte/word program algorithm ? embedded multi-block/chip erase algorithm ? status register po lling and toggle bits ? ready/busy output pin erase suspend and resume modes ? read and program another block during erase suspend unlock bypass program command ? faster production/batch programming temporary block unprotection mode low power consumption ? standby and automatic standby 100,000 program/erase cycles per block 20 years data retention ? defectivity below 1 ppm/year electronic signature ? manufacturer code: 0020h ? top device code m29f200bt: 00d3h ? bottom device code: M29F200BB: 00d4h ecopack ? packages available 44 1 tsop48 (n) 12 x 20mm so44 (m) www.st.com
contents m29f200bt, M29F200BB 2/39 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 address inputs (a0-a16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 data inputs/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 data inputs/outputs (dq8-dq14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 data input/output or address input (dq15a-1) . . . . . . . . . . . . . . . . . . . . 10 2.5 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 reset/block temporary unprotect (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9 ready/busy output (rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10 byte/word organization select (byte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 vss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.1 electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.2 block protection and blocks unprotection . . . . . . . . . . . . . . . . . . . . . . . 14 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.1 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.2 auto select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.3 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.4 unlock bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0.5 unlock bypass program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
m29f200bt, M29F200BB contents 3/39 4.0.6 unlock bypass reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0.7 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0.8 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0.9 erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0.10 erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 data polling bit (dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 toggle bit (dq6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 error bit (dq5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 erase timer bit (dq3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5 alternative toggle bit (dq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 appendix a block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
list of tables m29f200bt, M29F200BB 4/39 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. bus operations, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. bus operations, byte = v ih. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. commands, 16-bit mode, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. commands, 8-bit mode, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. program, erase times and program, erase endurance cycles (t a = 0 to 70c, ?40 to 85c or ?40 to 125c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. capacitance (ta = 25 c, f = 1 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 11. dc characteristics (t a = 0 to 70c, ?40 to 85c or ?40 to 125c). . . . . . . . . . . . . . . . . . . 29 table 12. read ac characteristics (ta = 0 to 70c, ?40 to 85c or ?40 to 125c) . . . . . . . . . . . . . . 30 table 13. write ac characteristics, write enable controlled (ta = 0 to 70 c, ?40 to 85 c or ?40 to 125 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. write ac characteristics, chip enable controlled (ta = 0 to 70 c, ?40 to 85 c or ?40 to 125 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. reset/block temporary unprotect ac characteristics (ta = 0 to 70 c, ?40 to 85 c or ?40 to 125 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . . . 34 table 17. so44 - 44 lead plastic small outline, 500 mils body width, package mechanical data . . . 35 table 18. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 19. top boot block addresses, m29f200bt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 20. bottom boot block addresses, M29F200BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
m29f200bt, M29F200BB list of figures 5/39 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6. ac testing input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 8. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 9. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 10. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. reset/block temporary unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline . . . . . . . . . . . 34 figure 13. so44 - 44 lead plastic small outline, 500 mils body width, package outline . . . . . . . . . . . 35
description m29f200bt, M29F200BB 6/39 1 description the m29f200b is a 2 mbit (256kb x8 or 128kb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be performed using a single 5v supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the m29f200b is fully backward compatible with the m29f200. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. each block can be protected independently to prevent accidental program or erase commands from modifying the memory. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to cont rol the memory is consistent with jedec standards. the blocks in the memory are asymmetrically arranged, see ta b l e 1 9 and ta bl e 2 0 , block addresses. the first or last 64 kbytes have been divided into four additional blocks. the 16 kbyte boot block can be used for small initialization code to start the microprocessor, the two 8 kbyte parameter blocks can be used for parameter storage and the remaining 32k is a small main block where the application may be stored. chip enable, output enable and write enable signals control the bus operation of the memory. they allow simple connection to most microprocessors, often without additional logic. the memory is offered in tsop48 (12 x 20mm) and so44 packages and it is supplied with all the bits erased (set to ?1?). in order to meet environmental requirements, st offers the m29f200b in ecopack ? packages. ecopack packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
m29f200bt, M29F200BB description 7/39 figure 1. logic diagram table 1. signal names name description direction a0-a16 address inputs inputs dq0-dq7 data inputs/o utputs input/outputs dq8-dq14 data inputs /outputs input/outputs dq15a?1 data input/output or address input input/output e chip enable input g output enable input w write enable input rp reset/block temporary unprotect input rb ready/busy output output byte byte/word organization select input v cc supply voltage supply v ss ground - nc not connected internally - ai02912 17 a0-a16 w dq0-dq14 v cc m29f200bt M29F200BB e v ss 15 g rp dq15a?1 byte rb
description m29f200bt, M29F200BB 8/39 figure 2. so connections g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 byte dq15a?1 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 w rb a4 nc rp a7 ai02914 m29f200bt M29F200BB 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 nc a8
m29f200bt, M29F200BB description 9/39 figure 3. tsop connections dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 nc a10 dq14 a2 dq12 dq10 dq15a?1 v cc dq4 dq5 a7 dq7 nc nc ai02913 m29f200bt M29F200BB 12 1 13 24 25 36 37 48 dq8 nc nc a1 nc a4 a5 dq1 dq11 g a12 a13 a16 a11 byte a15 a14 v ss e a0 rp v ss
signal descriptions m29f200bt, M29F200BB 10/39 2 signal descriptions see figure 1: logic diagram , and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a16) the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the internal state machine. 2.2 data inputs/outputs (dq0-dq7) the data inputs/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state machine. 2.3 data inputs/outputs (dq8-dq14) the data inputs/outputs output the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. 2.4 data input/output or address input (dq15a-1) when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15a?1 low will select the lsb of the word on the other addresses, dq15a?1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address inputs to include this pin when byte is low except when stated explicitly otherwise. 2.5 chip enable (e ) the chip enable, e , activates the memory, allowing bus read and bus write operations to be performed. when chip enable is high, v ih , all other pins are ignored. 2.6 output enable (g ) the output enable, g , controls the bus read operation of the memory.
m29f200bt, M29F200BB signal descriptions 11/39 2.7 write enable (w ) the write enable, w , controls the bus write operation of the memory?s command interface. 2.8 reset/block temporary unprotect (rp ) the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect al l blocks that have been protected. a hardware reset is achieved by holding reset/block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 15: reset/block temporary unprotect ac characteristics (ta = 0 to 70 c, ?40 to 85 c or ?40 to 125 c) and figure 11: reset/block temporary unprotect ac waveforms , for more details. holding rp at v id will temporarily unprotect the protec ted blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . 2.9 ready/busy output (rb ) the ready/busy pin is an open-drain output that can be used to identify when the memory array can be read. ready/busy is high-impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy becomes high-impedance. see table 15: reset/block temporary unprotect ac characteristics (ta = 0 to 70 c, ?40 to 85 c or ?40 to 125 c) and figure 11: reset/block temporary unprotect ac waveforms . during program or erase operations ready/busy is low, v ol . ready/busy will remain low during read/reset commands or hardware resets until the memory is ready to enter read mode. the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. 2.10 byte/word organization select (byte ) the byte/word organization select pin is used to switch between the 8-bit and 16-bit bus modes of the memory. when byte/word organization select is low, v il , the memory is in 8- bit mode, when it is high, v ih , the memory is in 16-bit mode. 2.11 v cc supply voltage the v cc supply voltage supplies the power for all operations (read, program, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from accidentally damaging the data during power up, power down and power surges. if the program/erase controller is
signal descriptions m29f200bt, M29F200BB 12/39 programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc4 . 2.12 vss ground the v ss ground is the reference for all voltage measurements.
m29f200bt, M29F200BB bus operations 13/39 3 bus operations there are five standard bus operations that control the device. these are bus read, bus write, output disable, standby and automatic standby. see ta bl e 2 and ta b l e 3 , bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. 3.1 bus read bus read operations read from the memory cells, or specific registers in the command interface. a valid bus read operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs /outputs will output the value, see figure 8: read mode ac waveforms , and table 12: read ac characteristics (ta = 0 to 70c, ?40 to 85c or ?40 to 125c) , for details of when the output becomes valid. 3.2 bus write bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole bus write operation. see figure 9 and figure 10 , write ac waveforms, and ta bl e 1 3 and ta bl e 1 4 , write ac characteristics, for details of the timing requirements. 3.3 output disable the data inputs/outputs are in the high impedance state when output enable is high, v ih . 3.4 standby when chip enable is high, v ih , the data inputs/outputs pins are placed in the high- impedance state and the supply current is reduced to the standby level. when chip enable is at v ih the supply current is reduced to the ttl standby supply current, i cc2 . to further reduce the supply current to the cmos standby supply current, i cc3 , chip enable should be held within v cc 0.2v. for standby current levels see table 11: dc characteristics (ta = 0 to 70c, ?40 to 85c or ?40 to 125c) . during program or erase oper ations the memory will contin ue to use the program/erase supply current, i cc4 , for program or erase operations until the operation completes.
bus operations m29f200bt, M29F200BB 14/39 3.5 automatic standby if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is reduced to the cmos standby supply current, i cc3 . the data inputs/outputs will still output data if a bus read operation is in progress. 3.6 special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus operations are intended for use by programming equipment and are not usually used in applications. they require v id to be applied to some pins. 3.6.1 electronic signature the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in ta b l e 2 and ta b l e 3 , bus operations. 3.6.2 block protection and blocks unprotection each block can be separately protected against accidental program or erase. protected blocks can be unprotected to allow data to be changed. there are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. for further information refer to application note an1122, applying protecti on and unprotection to m29 series flash. table 2. bus operations, byte = v il (1) 1. x = v il or v ih . operation e g w address inputs dq15a?1, a0-a16 data inputs/outputs dq14- dq8 dq7-dq0 bus read v il v il v ih cell address hi-z data output bus write v il v ih v il command address hi-z data input output disable x v ih v ih x hi-z hi-z standby v ih x x x hi-z hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih hi-z 20h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih hi-z d3h (m29f200bt) d4h (M29F200BB)
m29f200bt, M29F200BB bus operations 15/39 table 3. bus operations, byte = v ih (1) 1. x = v il or v ih . operation e g w address inputs a0-a16 data inputs/outputs dq15a?1, dq14-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih x hi-z standby v ih x x x hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih 0020h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih 00d3h (m29f200bt) 00d4h (M29F200BB)
command interface m29f200bt, M29F200BB 16/39 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. failure to observe a valid sequence of bus write operations will resu lt in the memory retu rning to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes depending on whether the memory is in 16- bit or 8-bit mode. see either ta bl e 4 , or ta b l e 5 , depending on the configuration that is being used, for a summary of the commands. 4.0.1 read/reset command the read/reset command returns the memory to its read mode where it behaves like a rom or eprom. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. if the read/reset command is issued during a block erase operation or following a programming or erase error then the memory will take up to 10 s to abort. during the abort period no valid data can be read from the memory. issuing a read/reset command during a block erase operation will leave invalid data in the memory. 4.0.2 auto select command the auto select command is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are required to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until another command is issued. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for stmicroelectronics is 0020h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29f200bt is 00d3h and for the M29F200BB is 00d4h. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a12-a16 specifying the address of the block. the other address bits may be set to either v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0-dq7, otherwise 00h is output. 4.0.3 program command the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write operations, the final write operation latches the address and data in the internal state machine and starts the program/erase controller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is ne ver read and no error condition is given. during the program operation the memory will i gnore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in ta bl e 6 . bus read operations during the program operation will ou tput the status register on the data inputs/outputs. see the section on the status register for more details.
m29f200bt, M29F200BB command interface 17/39 after the program operat ion has completed the memory will re turn to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. note that the program command cannot change a bit set at ?0? back to ?1?. one of the erase commands must be used to set all the bits in a block or in the whole me mory from ?0? to ?1?. 4.0.4 unlock bypass command the unlock bypass command is used in conjunction with the unlock bypass program command to program the memory. when the access time to the device is long (as with some eprom programmers) considerable time saving can be made by using these commands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been is sued the memory will only accept the unlock bypass program command and the unlock bypass reset command. the memory can be read as if in read mode. 4.0.5 unlock bypass program command the unlock bypass program command can be used to program one address in memory at a time. the command requires two bus write operations, the final write operation latches the address and data in the internal state machine and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the program operation using the program command. a protected block cannot be programmed; the operation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock bypass mode. see the program command for details on the behavior. 4.0.6 unlock b ypass reset command the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. 4.0.7 chip erase command the chip erase command can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation appears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands. it is not possible to issue any command to abort the operation. typical chip erase times are given in ta bl e 6 . all bus read operations during the chip erase operation will ou tput the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has complet ed the memory will return to the read mode, unless an error has occurred. when an error oc curs the memory will co ntinue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode.
command interface m29f200bt, M29F200BB 18/39 the chip erase command sets all of the bits in unprotected blocks of the memory to ?1?. all previous data is lost. 4.0.8 block erase command the block erase command can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate wit hin about 100s, leaving the data un changed. no erro r condition is given when protected blocks are ignored. during the block erase operat ion the memory will ignore a ll commands except the erase suspend and read/reset commands. typical block erase times are given in ta bl e 6 . all bus read operations during the block erase op eration will output the st atus register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has complete d the memory will return to the read mode, unless an error has occurred. when an error oc curs the memory will co ntinue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost. 4.0.9 erase suspend command the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend wi thin 15s of the er ase suspend command being issued. once the program/erase contro ller has stopped the memory will be set to read mode and the erase will be suspended. if the erase su spend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the er ase is suspended imme diately and will start immediately when the erase resu me command is issued. it will not be possible to select any further blocks for erasure after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. reading from blocks that are being erased will output the st atus register. it is also possible to enter the auto select mode: the memory will behave as in the auto select mode on all blocks until a read/reset command returns the memory to erase suspend mode.
m29f200bt, M29F200BB command interface 19/39 4.0.10 erase resume command the erase resume command must be used to restart the program/erase controller from erase suspend. an erase can be suspended and resumed more than once. table 4. commands, 16-bit mode, byte = v ih command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30
command interface m29f200bt, M29F200BB 20/39 table 5. commands, 8-bit mode, byte = v il (1)(2)(3) command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset (4) 1x f0 3 aaa aa 555 55 x f0 auto select (5) 3 aaa aa 555 55 aaa 90 program (6) 4 aaa aa 555 55 aaa a0 pa pd unlock bypass (7) 3 aaa aa 555 55 aaa 20 unlock bypass program (6) 2 x a0 pa pd unlock bypass reset (8) 2x 90 x 00 chip erase (6) 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase (6) 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase suspend (9) 1x b0 erase resume (10) 1x 30 1. x don?t care, pa program address, pd pr ogram data, ba any address in the block. 2. all values in the table are in hexadecimal. 3. the command interface only uses a?1, a0-a10 and dq0-dq 7 to verify the commands; a11-a16, dq8-dq14 and dq15 are don?t care. dq15a?1 is a?1 when byte is v il or dq15 when byte is v ih . 4. after a read/reset command, read the memory as normal until another command is issued. 5. after an auto select command, read manufacturer id, device id or bl ock protection status. 6. after a program, unlock bypass program, chip erase, or block erase command, read the status register until the program/erase controller completes and the memory return s to read mode. add additional blocks duri ng block erase command with additional bus write operations until the timeout bit is set. 7. after the unlock bypass command, issue unlock bypass program or unlock bypass reset commands. 8. after the unlock bypass reset command read the memo ry as normal until another command is issued. 9. after the erase suspend command, read non-erasing memory blocks as normal, issue auto select and program commands on non-erasing blocks as normal. 10. after the erase resume command the suspended erase oper ation resumes, read the status register until the program/erase controller completes and the memory returns to read mode.
m29f200bt, M29F200BB command interface 21/39 table 6. program, erase times and program, erase endurance cycles (t a = 0 to 70c, ?40 to 85c or ?40 to 125c) parameter min typ (1) typical after 100k w/e cycles (1) max unit chip erase (all bits in the memory set to ?0?) 0.8 0.8 s chip erase 2.5 2.5 10 s block erase (64 kbytes) 0.6 0.6 4 s program (byte or word) 8 8 150 s chip program (byte by byte) 2.3 2.3 9 s chip program (word by word) 1.2 1.2 4.5 s program/erase cycles (per block) 100,000 cycles 1. t a = 25c, v cc = 5v.
status register m29f200bt, M29F200BB 22/39 5 status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase suspend when an address within a block being erased is accessed. the bits in the status register are summarized in table 7: status register bits . 5.1 data polling bit (dq7) the data polling bit can be used to identi fy whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bi t outputs the compleme nt of the bit being programmed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the address just programmed output dq7, not its complement. during erase operations the data polling bit outp uts ?0?, the complement of the erased state of dq7. after successful completion of the erase operation the memory returns to read mode. in erase suspend mode the da ta polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from a ?0? to a ?1? when the program/erase controller has suspended the erase operation. figure 4: data polling flowchart , gives an example of how to us e the data polling bit. a valid address is the address being programmed or an address within the block being erased. 5.2 toggle bit (dq6) the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations at any addres s. after successful completion of the operation the memory returns to read mode. during erase suspend mo de the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop togglin g when the program/erase controller has suspended the erase operation. figure 5: data toggle flowchart , gives an example of how to use the data toggle bit. 5.3 error bit (dq5) the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued
m29f200bt, M29F200BB status register 23/39 before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set at ?0? back to ?1? and attempting to do so may or may not set dq5 at ?1?. in bo th cases, a successive bus read operation will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. 5.4 erase timer bit (dq3) the erase timer bit can be used to identify the start of program/erase controller operation during a block erase command. once the program/erase controller starts erasing the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be eras ed may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. 5.5 alternative toggle bit (dq2) the alternative toggle bit can be used to monitor the program/erase controller during erase operations. the alternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bi t changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to addresses within blocks not be ing erased will output the me mory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the error. the alternative toggle bit changes from ?0? to ?1? to ?0 ?, etc. with successive bus read operations from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased correctly.
status register m29f200bt, M29F200BB 24/39 table 7. status register bits (1) 1. unspecified data bits should be ignored. operation address dq7 dq6 dq5 dq3 dq2 rb program any address dq7 to g g l e 0 ? ? 0 program during erase suspend any address dq7 to g g l e 0 ? ? 0 program error any address dq7 to g g l e 1 ? ? 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no to g g l e 0 ? toggle 1 non-erasing block data read as normal 1 erase error good block address 0 toggle 1 1 no toggle 0 faulty block address 0 toggle 1 1 toggle 0
m29f200bt, M29F200BB status register 25/39 figure 4. data polling flowchart read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
status register m29f200bt, M29F200BB 26/39 figure 5. data toggle flowchart read dq6 start read dq6 twice fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
m29f200bt, M29F200BB maximum rating 27/39 6 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device relia bility. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality documents. table 8. absolute maximum ratings (1) 1. except for the operating temperature r ange, stresses above those listed in the table 8: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. refer also to the st microelectronics sure progr am and other relevant quality documents. symbol parameter value unit t a ambient operating temperature (temperature range option 1) 0 to 70 c ambient operating temperature (temperature range option 6) ?40 to 85 c ambient operating temperature (temperature range option 3) ?40 to 125 c t bias temperature under bias ?50 to 125 c t stg storage temperature ?65 to 150 c v io (2) 2. minimum voltage may undershoot to ?2v during transit ion and for less than 20ns during transitions. input or output voltage ?0.6 to 6 v v cc supply voltage ?0.6 to 6 v v id identification volt age ?0.6 to 13.5 v
dc and ac parameters m29f200bt, M29F200BB 28/39 7 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 9: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 6. ac testing input output waveform table 9. operating and ac measurement conditions parameter m29f200b 45 / 50 70 / 90 ac test conditions high speed standard load capacitance (c l ) 30pf 100pf input rise and fall times 10ns 10ns input pulse voltages 0 to 3v 0.45 to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2.0v table 10. capacitance (t a = 25 c, f = 1 mhz) (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf ai01275b 3v high speed 0v 1.5v 2.4v standard 0.45v 2.0v 0.8v
m29f200bt, M29F200BB dc and ac parameters 29/39 figure 7. ac testing load circuit table 11. dc characteristics (t a = 0 to 70c, ?40 to 85c or ?40 to 125c) symbol parameter test condition min typ (1) 1. t a = 25c, v cc = 5v. max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 620ma i cc2 supply current (standby) ttl e = v ih 1ma i cc3 supply current (standby) cmos e = v cc 0.2v, rp = v cc 0.2v 30 100 a i cc4 (2) 2. sampled only, not 100% tested. supply current (program/erase) program/erase controller active 20 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 2 v cc +0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage ttl i oh = ?2.5ma 2.4 v output high voltage cmos i oh = ?100 av cc ?0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 a v lko (2) program/erase lockout supply voltage 3.2 4.2 v ai03027 1.3v out c l = 30pf or 100pf c l includes jig capacitance 3.3k ? 1n914 device under test
dc and ac parameters m29f200bt, M29F200BB 30/39 figure 8. read mode ac waveforms table 12. read ac characteristics (ta = 0 to 70c, ?40 to 85c or ?40 to 125c) symbol alt parameter test condition m29f200b unit 45 50 70 / 90 t avav t rc address valid to next address valid e = v il , g = v il min455070ns t avqv t acc address valid to output valid e = v il , g = v il max455070ns t elqx (1) t lz chip enable low to output transition g = v il min000ns t elqv t ce chip enable low to output valid g = v il max455070ns t glqx (1) t olz output enable low to output transition e = v il min000ns t glqv t oe output enable low to output valid e = v il max253030ns t ehqz (1) t hz chip enable high to output hi-z g = v il max151820ns t ghqz (1) t df output enable high to output hi-z e = v il max151820ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min000ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 5 ns t blqz t flqz byte low to output hi-z max 15 15 20 ns t bhqv t fhqv byte high to output valid max 30 30 30 ns 1. sampled only, not 100% tested. ai02915 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a16/ a?1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte
m29f200bt, M29F200BB dc and ac parameters 31/39 figure 9. write ac waveforms, write enable controlled table 13. write ac characteristics, write enable controlled (t a = 0 to 70 c, ?40 to 85 c or ?40 to 125 c) symbol alt parameter m29f200b unit 45 50 70 / 90 t avav t wc address valid to next address valid min 45 50 70 ns t elwl t cs chip enable low to write enable low min 0 0 0 ns t wlwh t wp write enable low to write enable high min 40 40 45 ns t dvwh t ds input valid to write enable high min 25 25 30 ns t whdx t dh write enable high to input transition min 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 ns t whwl t wph write enable high to write enable low min 20 20 20 ns t avwl t as address valid to write enable low min 0 0 0 ns t wlax t ah write enable low to address transition min 40 40 45 ns t ghwl output enable high to write enable low min 0 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 0 ns t whrl (1) t busy program/erase valid to rb low max 30 30 30 ns t vchel t vcs v cc high to chip enable low min 50 50 50 s 1. sampled only, not 100% tested. ai01991 e g w a0-a16/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
dc and ac parameters m29f200bt, M29F200BB 32/39 figure 10. write ac waveforms, chip enable controlled table 14. write ac characteristics, chip enable controlled (t a = 0 to 70 c, ?40 to 85 c or ?40 to 125 c) symbol alt parameter m29f200b unit 45 50 70 / 90 t avav t wc address valid to next address valid min 45 50 70 ns t wlel t ws write enable low to chip enable low min 0 0 0 ns t eleh t cp chip enable low to chip enable high min 40 40 45 ns t dveh t ds input valid to chip enable high min 25 25 30 ns t ehdx t dh chip enable high to input transition min 0 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 0 ns t ehel t cph chip enable high to chip enable low min 20 20 20 ns t avel t as address valid to chip enable low min 0 0 0 ns t elax t ah chip enable low to address transition min 40 40 45 ns t ghel output enable high chip enable low min 0 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 30 30 ns t vchwl t vcs v cc high to write enable low min 50 50 50 s 1. sampled only, not 100% tested. ai01992 e g w a0-a16/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
m29f200bt, M29F200BB dc and ac parameters 33/39 figure 11. reset/block temporary unprotect ac waveforms table 15. reset/block temporary unprotect ac characteristics (t a = 0 to 70 c, ?40 to 85 c or ?40 to 125 c) symbol alt parameter m29f200b unit 45 50 70 / 90 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min000ns t plpx t rp rp pulse width min 500 500 500 ns t plyh (1) t ready rp low to read mode max 10 10 10 s t phphh (1) t vidr rp rise time to v id min 500 500 500 ns 1. sampled only, not 100% tested. ai02931 rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl
package mechanical m29f200bt, M29F200BB 34/39 8 package mechanical figure 12. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline 1. drawing is not to scale. tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp table 16. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 305305
m29f200bt, M29F200BB package mechanical 35/39 figure 13. so44 - 44 lead plastic small outline, 500 mils body width, package outline 1. drawing is not to scale. e1 44 e d c e 1 22 23 b so-f l a1 a ddd a2 l1 table 17. so44 - 44 lead plastic small outline, 500 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 3.00 0.118 a1 0.10 0.004 a2 2.69 2.56 2.79 0.106 0.101 0.110 b 0.35 0.50 0.014 0.020 c 0.18 0.28 0.007 0.011 d 28.50 28.37 28.63 1.122 1.117 1.127 ddd 0.10 0.004 e 16.03 15.77 16.28 0.631 0.621 0.641 e1 12.60 12.47 12.73 0.496 0.491 0.501 e 1.27 ? ? 0.050 ? ? l 0.79 0.031 l1 1.73 0.068 88 n44 44
part numbering m29f200bt, M29F200BB 36/39 9 part numbering the last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 18. ordering information scheme example: M29F200BB 50 n 1 t device type m29 operating voltage f = v cc = 5v 10% device function 200b = 2 mbit (256kb x8 or 128kb x16), boot block array matrix t = top boot b = bottom boot speed 45 = 45 ns 50 = 50 ns (1) 1. 50ns speed devices are only available in M29F200BB in temperature range option 3. 70 = 70 ns 90 = 90 ns package n = tsop48: 12 x 20 mm m = so44 500mm width temperature range 1 = 0 to 70 c 3 = ?40 to 125 c 6 = ?40 to 85 c option blank = standard packing t = tape & reel packing e = ecopack package, standard packing f = ecopack package, tape & reel packing
m29f200bt, M29F200BB block addresses 37/39 appendix a block addresses table 19. top boot block addresses, m29f200bt # size (kbytes) address range (x8) address range (x16) 6 16 3c000h-3ffffh 1e000h-1ffffh 5 8 3a000h-3bfffh 1d000h-1dfffh 4 8 38000h-39fffh 1c000h-1cfffh 3 32 30000h-37fffh 18000h-1bfffh 2 64 20000h-2ffffh 10000h-17fffh 1 64 10000h-1ffffh 08000h-0ffffh 0 64 00000h-0ffffh 00000h-07fffh table 20. bottom boot block addresses, M29F200BB # size (kbytes) address range (x8) address range (x16) 6 64 30000h-3ffffh 18000h-1ffffh 5 64 20000h-2ffffh 10000h-17fffh 4 64 10000h-1ffffh 08000h-0ffffh 3 32 08000h-0ffffh 04000h-07fffh 2 8 06000h-07fffh 03000h-03fffh 1 8 04000h-05fffh 02000h-02fffh 0 16 00000h-03fffh 00000h-01fffh
revision history m29f200bt, M29F200BB 38/39 10 revision history table 21. document revision history date revision changes july 1999 1.0 first issue 10/08/99 2.0 chip erase max. specification added ( ta bl e 6 ) block erase max. specification added ( ta bl e 6 ) program max. specification added ( ta b l e 6 ) chip program max. specification added ( ta b l e 6 ) i cc1 and i cc3 typ. specification added ( ta bl e 1 1 ) i cc3 test condition changed ( ta bl e 1 1 ) 07/28/00 3.0 new document template document type: from preliminary data to data sheet status register bit dq5 clarification data polling flowchart diagram change ( figure 4 ) data toggle flowchart diagram change ( figure 5 ) 19-sep-2005 4.0 document restructured. table 18: ordering information scheme : standard package added and ecopack version added for both standard package and tape & reel packing. note 1 modified. 55ns speed class replaced by 50ns. tsop48 mechanical data updated, and so44 525mm body width changed to so44 500mm body width. 22-mar-2007 5 document restructured. so44 package code changed to ?m? in section : features and in ta bl e 1 8 : ordering information scheme .
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